library verilog;
use verilog.vl_types.all;
entity piano_top is
    port(
        clk32mHz        : in     vl_logic;
        handtoauto      : in     vl_logic;
        index1          : in     vl_logic_vector(7 downto 0);
        code1           : out    vl_logic_vector(6 downto 0);
        high1           : out    vl_logic;
        spkout          : out    vl_logic
    );
end piano_top;
